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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L Series
TMP93CF76 TMP93CF77 TMP93CW76 TMP93CU76 TMP93CT76
Preface
Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions.
**CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts (INT0, INT1), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fc or fs) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
TMP93CF76/CF77/CW76/CU76/CT76
CMOS 16-Bit Microcontroller
TMP93CF76/CF77/CW76/CU76/CT76 1. Outline and Feature
TMP93CF76/CF77/CW76/CU76/CT76 are a high-speed advanced 16-bit microcontroller developed for application with VCR system control, software servo motor control, VFT driver and timer control. In addition to basics such as I/O ports, the TMP93CF76/CF77/CW76/CU76/CT76 have highspeed/high-precision signal measuring circuit, PWM (Pulse-Width-Modulator) and high-precision real timing pulse generator. The device characteristics are as follows: (1) Original 16-bit CPU (900/L CPU) TLCS-90 instruction mnemonic upward compatible 16 Mbyte linear address space General-purpose registers and register bank system 16-bit multiplication/division and bit transfer/arithmetic instructions High-speed micro DMA: 4 channels (2 s/2 byte at 16 MHz) (2) Minimum instruction execution time: 250 ns at 16 MHz (3) Internal ROM:
TMP93CF76 TMP93CF77 TMP93CW76 TMP93CU76 TMP93CT76 192 KB 160 KB 128 KB 96 KB 72 KB
(4) Internal RAM:
TMP93CF76 TMP93CF77 TMP93CW76 TMP93CU76 TMP93CT76
4.0 KB 4.0 KB 2.5 KB 2.5 KB 2.0 KB
000707EBP1
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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(5) 20-bit time-base-counter (TBC) Free running counter Accuracy: 125 ns (at fc Overflow: 131 ms (at fc (6) 8-bit timer (TC0): 1 channel For CTL linear time counter (7) 16-bit timer (TC1 to 5): 5 channels C.sync count, capstan FG count, general: 3 channels (8) Timing pulse generator (TPG): 2 channels (16-bit timing data (16-bit timing data 6-bit output data) with 8-stages FIFO 4-bit output data) : 1 channel : 1 channel 16 MHz) 16 MHz)
Accuracy: 500 ns (at 16 MHz) (9) Pulse width modulation outputs (PWM) 14-bit PWM: 3 channels (for controlling capstan, drum and tuner) 8-bit PWM: 1 channel (for controlling volume ) Carrier frequency: 31.25 kHz (at 16 MHz) (10) 24-bit time base counter capture circuit (Capture 0) (18-bit timing data 6 bit trigger data) with 8-stages FIFO: 1 channel Capture input sources: Remote-control-input (RMTIN), V.sync, CTL, Drum-PG, general (1 channel) Accuracy: 500 ns (at 16 MHz) (11) 17-bit time base counter capture circuit (Capture 1/2) (16-bit timing data 1-bit trigger data): 2 channels Capture input sources: Drum-FG, Capstan-FG Accuracy: 125 ns (at 16 MHz) (12) VISS/VASS detection circuit (VISS/VASS) CTL duty detection VASS data 16-bit latch (13) Composite-sync-signal (C.sync) input Vertical-sync-signal (V.sync) separation Horizontal-sync-signal (H.sync) separation (14) Head Amp switch/Color Rotary control (HA/CR) (15) Pseudo-V/H generator (PV/PH) (16) 8-bit AD converter (ADC): 10 channels Conversion speed: 95 states (11.8 s at 16 MHz) (17) Serial Channel (SIO): 1channel (18) Serial bus I/F I2C bus with 8-stages FIFO: 1 channel/2 ports (19) Watch dog timer (WDT)
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(20) Interrupt controller (INTC) CPU: 8 sources SWI instruction and illegal instruction 7-level priority can be set. Internal: 17 sources External: 5 sources (21) I/O ports 67 I/O ports (multiplexed functional pins.) High Break Down Voltage PortE, F are Included: 14 I/O ports 8 input ports (P40/AIN2 to P47/AIN9) 10 output ports PC0/G0 to PC7/G7, PD0/G8 to PD1/G9: High Break Down Voltage (22) Standby function: 4 halt modes (RUN, IDLE2, IDLE1, STOP) (23) System clock function Dual clock operation 16 MHz (High-speed: normal)/32 kHz (Low-speed:slow) ... 17-bit Real Time Counter built in (24) Operating Voltage Vcc Vcc (25) Package 100 pin QFP 14 mm 20 mm (Pin pitch: 0.65 mm) Product name: P-QFP100-1420-0.65A 2.7 to 5.5 V (at 32 kHz) 4.5 to 5.5 V (at 16 MHz)
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DVCC DGND P73/SDA0 P74/SCL0 P75/AIN0/SDA1 P76/AIN1/SCL1 to AD P51/SO P52/SCK for P50 (SI) PWM0 PWM1 PA3/PWM2 14-BIT PWM (3CH) SIO I2 C bus I/F (IIC)
XWA XBC XDE XHL XIX XIY XIZ XSP 32 bit SR PC F W B D H IX IY IZ SP L A 900/L CPU
High frequency OSC (16 MHz)
X1 X2
Real Time Counter (RTC)
CPU INT
Low frequency OSC (32 kHz)
PB0/XT1 PB1/XT2 TEST CLK RESET
Interrupt Controller
P54/INT0 P53/INT1 TEST1 TEST2 TEST3 (NC)
8-BIT PWM (1CH) to PWM3 (VFT Driver) PD0 to 1/G8 to 9 PC0 to 7/G0 to 7 PC0 to 5/S8 to 13 PE0 to 7/S0 to 7 Vkk 8-Bit Timer (TC0) P96/TO1/TPG10 P52/INT2/TI1(TI0) P51/INT3/TI2 (TI4) P50/INT4/TI3 (TI5)/SI 16-Bit Timer (TC1) 16-Bit Timer (TC2) 16-Bit Timer (TC3) 16-Bit Timer (TC4) 16-Bit Timer (TC5) to SIO P93/TPG03 P97/TPG11 Timing Pulse Generater (TPG) P91/TPG01/ VASWP P90/TP0/TPG00 P92/TP1 P94/CR P94/HA P87/COMPIN Head Amp SW Color Rotary VISS/VASS CTL Duty Detector Capture (Capture0, 1, 2)
VS
INT2, 3, 4 Others INT
RAM
(2.0/2.5/4.0 KB) Port 2 P20 to 27 P10 to17 P00 to 07
Port D Port C Port F Port E
ROM
(72/96/128/ 166/192 KB)
Port 1 Port 0
Watchdog Timer (WDT) Time Base Timer (TBC)
for P75 (AIN0) P76 (AIN1) 8 BIT AD Converter (10 CH) ADREF P40 to 47/AIN2 to 9 ADGND
V-Separation
C-sync
P86/CSYNCIN
RMTU, RMTD EXT
RMT-Input External-Input
P82/RMTIN P83/EXT/TO1
CTL, CFG, DFG, DPG CFGTM
P84/DPGIN Capture Input (CAPIN) P85/CFGIN P81/DFGIN P80/CTLIN
PCTL
HS
PV/PH for 8-BIT PWM
PA0/PWM3/ PVPH
Figure 1.1 TMP93CF76/CF77/CW76/CU76/CT76 block diagram
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2.
Pin Assignment and Functions
The assignment of input and output pins for the TMP93CF76/CF77/CW76/CU76/CT76, their names and functions are described below.
2.1
Pin Assignment
Figure 2.1.1 shows pin assignment of the TMP93CF76/CF77/CW76/CU76/CT76. P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 TEST3 P23 P24 P25 P26 P27 PE0/S0 PE1/S1 PE2/S2 PE3/S3 PE4/S4 PE5/S5 PE6/S6 PE7/S7 PF0/S8 PF1/S9 PF2/S10 PF3/S11 PF4/S12 PF5/S13 PC0/G0 PC1/G1 PC2/G2 PC3/G3 PC4/G4 PC5/G5 PC6/G6 PC7/G7 PD0/G8 PD1/G9 VKK 1
100
95
90
85
80
TEST2 TEST1 PB1/XT2 PB0/TX1
RESET TEST
5 75
10 70
15 65
20
60
25 55
30
35
40
45
50
X2 X1 DGND CLK P54/INT0 P53/INT1 P52/INT2/TI1/TI0/SCK P51/INT3/TI2/TI4/SO P50/INT4/TI3/TI5/SI ADREF ADGND P47/AIN9 P46/AIN8 P45/AIN7 P44/AIN6 P43/AIN5 P42/AIN4 P41/AIN3 P40/AIN2 P76/AIN1/SCL1 P75/AIN0/SDA1 P74/SCL0 P73/SDA0 P87/COMPIN
DVCC PA0/PWM3/PVPH PA3/PWM2 PWM0 PWM1 P90/TP0/TPG00 P91/TPG01/VASWP P92/TP1 P93/TPG03 P94/CR P95/HA P96/TO1/TPG10 P97/TPG11 P80/CTLIN P81/DFGIN P82/RMTIN P83/EXT/TO1 P84/DPGIN P85/CFGIN P86/CSYNCIN Figure 2.1.1 Pin assignment (100-pin QFP)
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2.2
Pin Names and Functions
The names of input/output pins and their functions are described below.
Table 2.2.1 Pin names and function (1/3) Pin name
P00 to P07 P10 to P17 P20 to P27 P40 to P47 AIN2 to AIN9 P50 INT4 TI3 TI5 SI P51 INT3 TI2 TI4 SO P52 INT2 TI1 TI0 SCK P53 INT1 P54 INT0 P73 SDA0 P74 SCL0 P75 SDA1 AIN0 P76 SCL1 AIN1 P80 CTLIN P81 DFGIN
Number of pins
8 8 8 8 1
I/O
I/O I/O I/O Input Input I/O Input Input Input Input I/O Input Input Input Output I/O Input Input Input I/O I/O Input I/O Input I/O I/O I/O I/O I/O I/O Input I/O I/O Input I/O Input I/O Input port0: I/O ports port1: I/O ports port2: I/O ports
Functions
port4: Input ports Analog input: Input to AD converter Port50: I/O port (schmitt input) External Interrupt request input 4: Rising edge/Falling edge programable 16-bit timer3 (TC3) Input 3 16-bit timer5 (TC5) input 5 SIO received data Port51: I/O port (schmitt input) External Interrupt request input 3: Rising edge/Falling edge programable 16-bit timer2 (TC2): Input 2 16-bit timer4 (TC4): input 4 SIO sending data Port52: I/O port (schmitt input) External Interrupt request input 2: Rising edge/Falling edge programable 16-bit timer1 (TC1) Input 1 8-bit Timer0 (TC0) Input 0 SIO clock line Port53: I/O port (schmitt input) External Interrupt request pin1: Rising edge/Level programable Port54: I/O port (schmitt input) External Interrupt request pin0: Rising edge/Falling edge programable Port73: I/O port (schmitt input, Push-pull or open-drain output selectable) I2C bus SDA0 line Port74: I/O port (schmitt input, Push-pull or open-drain output selectable) I2C bus SCL0 line Port75: I/O port (schmitt input, Push-pull or open-drain output selectable) I2C bus SDA1 line Analog input 0: Analog input signal for AD converter Port76: Input port (schmitt input, Push-pull or open-drain output selectable) I2C bus SCL1 line Analog input 1: Analog input signal for AD converter Port80: I/O port (schmitt input) CTL Capture input (Capture 0) Port81: I/O port (schmitt input) DFG Capture input (Capture 1)
1
1
1
1
1 1 1
1
1 1
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Table 2.2.1 Pin names and function (2/3) Pin name
P82 RMTIN P83 EXT TO1 P84 DPGIN P85 CFGIN P86 CSYNCIN P87 COMPIN P90 TP0 TPG00 P91 VASWP TPG01 P92 TP1 P93 TPG03 P94 CR P95 HA P96 TO1 TPG10 P97 TPG11 PA0 PVPH PWM3 PA3 PWM2
Number of pins
1 1
I/O
I/O Input I/O Input Output I/O Input I/O Input I/O Input I/O Input I/O Output Output I/O Output Output I/O Output I/O Output I/O Output I/O Output I/O Output Output I/O Output I/O Output Output I/O Output
Functions
Port82: I/O port (schmitt input) Remote Control Signal Capture input Port83: I/O port (schmitt input) External Capture input (Capture 0) Timer Out 1 Port84: I/O port (schmitt input) DPG Capture input (Capture 0) Port85: I/O port (schmitt input) CFG Capture input (Capture 2) Port86: I/O port (schmitt input) C.sync Capture input Port87: I/O port (schmitt input) Envelope Comparate Input (to HA/CR) Port90: I/O port (Push-pull or open-drain output selectable) Timing Pulse output 0 TPG00: TPG0 output Port91: I/O port (Push-pull or open-drain output selectable) Video/Audio head switching control signal output TPG01: TPG0 output Port92: I/O port (Push-pull or open-drain output selectable) Timing Pulse output 1 Port93: I/O port (Push-pull or open-drain output selectable) TPG03: TPG0 output Port94: I/O port (Push-pull or open-drain output selectable) Color Rotary Output Port95: I/O port (Push-pull or open-drain output selectable) Head Amp Switching Control Output Port96: I/O port (Push-pull or open-drain output selectable) Timer Out 1 TPG10: TPG1 output Port97: I/O port (Push-pull or open-drain output selectable) TPG11: TPG1 output PortA0: I/O port PVPH 3-state Output PWM(8 bits) output 3 PortA3: I/O port (Push-pull or open-drain output selectable) PWM(14 bits) output 2
1 1 1 1 1
1
1 1 1 1 1
1 1
1
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Table 2.2.1 Pin names and function (3/3) Pin name
PWM0 PWM1 PB0 XT1 PB1 XT2 PC0 to PC7 G0 to G7 PD0,1 G8, 9 PE0 to PE7 S0 to S7 PF0 to PF5 S8 to S13 TEST1 TEST2 TEST3(NC) CLK
Number of pins
1 1 1 1 8 2 8 6 1 1 1 1
I/O
Output Output I/O Input I/O Output Output Output Output Output I/O Output I/O Output Output Input Output Output
Functions
PWM(14 bits) output 0 (Push-pull or open-drain output selectable) PWM(14 bits) output 1 (Push-pull or open-drain output selectable) PortB0: I/O port (Open-drain Output) Low Frequency Oscillator connecting pin PortB1: I/O port (Open-drain Output) Low Frequency Oscillator connecting pin PortC: Output (High break down voltage outputs with pull-down resistor) Grid Drivers PortD: Output (High break down voltage outputs with pull-down resistor) Grid Drivers PortE: I/O ports (High break down voltage outputs with pull-down resistor) Segment Drivers PortF: I/O ports (High break down voltage outputs with pull-down resistor) Segment Drivers TEST1 should be connected with TEST2 pin. TEST3 should be open connection. Clock output: Output (System Clock 2) clock. Pulled-up during reset. Can be set to output disable for reducing noise. (Initial Disable) Test pin: Always set to "Vcc" level Reset: Initializes LSI. (with pull-up resistor) High Frequency Oscillator connecting pins (16 MHz) High Frequency Oscillator connecting pins (16 MHz) VFT Driver power supply pin Power supply pin GND pin (0 V) Reference voltage input for AD converter GND pin for AD converter
TEST RESET
1 1 1 1 1 1 1 1 1
Input Input Input Output
X1 X2 VKK DVCC DGND ADREF ADGND
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3.
Operation
This section describes the functions TMP93CF76/CF77/CW76/CU76/CT76 devices. and basic operational blocks of
See the "7. Points of Concern and Restrictions" for the using notice and restrictions for each block.
3.1
CPU
TMP93CF76/CF77/CW76/CU76/CT76 devices have a built-in high-performance 16-bit CPU (900/L CPU). (For CPU operation, see TLCS-900/L CPU in the previous section). This section describes CPU functions unique to the TMP93CF76/CF77/CW76/CU76/CT76 that are not described in the previous section.
3.1.1
Reset
To reset the TMP93CF76/CF77/CW76/CU76/CT76, the RESET input must be kept at 0 for at least 10 system clocks. (1.25 s at 16 MHz) within the operating voltage range and with a stable oscillation. When reset is accepted, the CPU sets as follows: Program Counter (PC) according to Reset Vector that is stored FFFF00H to FFFF02H. PC (7:0) PC (15:8) PC (23:16) stored data in location FFFF00H stored data in location FFFF01H stored data in location FFFF02H
Stack pointer (XSP) for system mode to 100H. IFF2 to 0 bits of status register to 111. (Sets mask register to interrupt level 7.) MAX bit of status register to 1. (Sets to maximum mode) Bits RFP2 to 0 of status register to 000. (Sets register banks to 0.) When reset is released, instruction execution starts from PC (reset vector). CPU internal registers other than the above are not changed. When reset is accepted, processing for built-in I/Os, ports, and other pins is as follows Initializes built-in I/O registers as per specifications. Sets port pins (including pins also used as built-in I/Os) to general-purpose input/output port mode.
Note:
By resetting, register in the CPU except program counter (PC), status register (SR) and stack pointer (XSP) and the data in internal RAM are not changed.
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3.2
Memory Map
Figure 3.2.1 is a memory map of the TMP93CF76/CF77/CW76/CU76/CT76.
000000H Internal I/O (144 byte) 000090H
000000H Internal I/O (144 byte) 000090H Internal RAM (4.0 Kbyte)
000000H Internal I/O (144 byte) 000090H Internal RAM (2.5 Kbyte) 000100H Direct Area (n)
000100H Internal RAM (4.0 Kbyte)
000100H
000A90H
001090H
001090H 64K-byte Area (nn)
FD0000H FD8000H FE0000H
Internal ROM (192 Kbyte)
Internal ROM (160 Kbyte)
Internal ROM (128 Kbyte)
FFFF00H Interrupt Vector Table Area (256 byte) FFFFFFH TMP93CF76
FFFF00H Interrupt Vector Table Area (256 byte) FFFFFFH TMP93CF77
FFFF00H Interrupt Vector Table Area (256 byte) FFFFFFH TMP93CW76
16-Mbyte Area (R) ( R) (R ) (R R8/16) (R d8/16) (nnn)
Internal Area
Figure 3.2.1 Memory map (1/2)
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000000H Internal I/O (144 byte) 000090H Internal RAM (2.5 Kbyte) 000100H
000000H Internal I/O (144 byte) 000090H Internal RAM (2.0 Kbyte) 000100H 000890H Direct Area (n)
000A90H
64K-byte Area (nn)
FE8000H FEE000H
Internal ROM (96 Kbyte)
Internal ROM (72 Kbyte)
FFFF00H Interrupt Vector Table Area (256 byte) FFFFFFH TMP93CU76
FFFF00H Interrupt Vector Table Area (256 byte) FFFFFFH TMP93CT76
16-Mbyte Area (R) ( R) (R ) (R R8/16) (R d8/16) (nnn)
Internal Area
Figure 3.2.1 Memory map (2/2)
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4.
4.1
Electrical Characteristics
Absolute Maximum Rating
Parameter
Power Supply Voltage Input Voltage Output Voltage (except PC, PD, PE, PF) Output Voltage (PC, PD, PE, PF) Output Current (except PC, PD, PE, PF) (per 1 pin) Output Current (PC, PD) (per 1 pin) Output Current (PE, PF) (per 1 pin) Output Current (per 1 pin) Output Current (total except PC, PD, PE, PF) Output Current (total of PC, PD, PE, PF) Output Current (total) Power Dissipation (Ta Soldering Temperature Storage Temperature Operating Temperrature 70C)
Symbol
Vcc VIN VOUT1 VOUT2 IOH1 IOH2 IOH3 IOL IOH1 IOH2 IOL PD Tsolder Tstg Topr
Rating
0.5 to 6.5 0.5 to Vcc 0.5 0.5 to Vcc 0.5 Vcc 40 3.2 25 15 3.2 40 120 120 600 260 65 to 150 20 to 70
Unit
V
mA
mW C
Note:
The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
4.2
DC Characteristics (1/2)
Ta 20 to 70C
Parameter
Power Supply Voltage P0, P1, P2, P4, P9, PA, PB, PE, PF RESET , P5, P7, P8
TEST
Symbol
Vcc VIL1 (CMOS) VIL2 (Schmitt) VIL3 (Fixed) VIL4 (Xtal) VIH1 (CMOS) VIH2 (Schmitt) VIH3 (Fixed) VIH4 (Xtal) fc fs
Condition
4 to 16 MHz 30 to 34 kHz
Min
4.5 2.7
Typ.
Max
5.5 0.3 Vcc 0.25 Vcc
Unit
V
Input Low Voltage
0.3 0.3 0.2 Vcc Vcc 2.7 to 5.5 V 0.7 Vcc 0.75 Vcc Vcc Vcc 0.3 0.3 V
X1 P0, P1, P2, P4, P9, PA, PB, PE, PF RESET , P5, P7, P8
TEST
Input High Voltage
X1
0.8 Vcc
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4.2
DC Characteristics (2/2)
Ta 20 to 70C
Parameter
Output Low Voltage Output High Voltage PE, PF PC, PD Input Leakage Current Output Leakage Current Power Down Voltage
RESET
Symbol
VOL VOH VOH1 IOH ILI ILO VSTOP RRST CIO VTH
Condition
IOL 1.6 mA (Vcc 2.7 to 5.5 V) IOH (Vcc IOH (Vcc 400 A 2.7 to 5.5 V) 700 A 4.5 to 5.5 V)
Min
Typ.
Max
0.45
Unit
V
2.4 V 4.1 5 15 mA 0.02 0.05 2.0 50 80 5 A 10 6.0 150 200 10 1.0 30 50 28 25 8 80 45 40 25 10 A mA V k pF V
Vcc 4.5 V VOH 2.4 V 0.0 0.2 VIL2 VIH2 Vcc Vcc osc Vin Vin VCC VCC -0.2
0.2 VCC, 0.8 VCC 5 V 10% 3 V 10% 1 MHz/100 mVp-p
Pull Up Resistor Pin Capacitance Schmitt Width RESET , P5,P7,P8 NORMAL RUN IDLE2 IDLE1 SLOW RUN IDLE2 IDLE1 STOP
Vcc 5 V 10% fc 16 MHz Icc
18 15 5 50 30 25 12 0.2
Vcc 3 V 10% fs 32.768 kHz (typ: VCC 3.0 V) Vcc 2.7 to 5.5 V
Note 1: Typical value are for Ta
25C and Vcc
5 V unless otherwise noted.
Note 2: Icc measurement conditions (NORMAL,SLOW). Only CPU is operational;output pins are open and input pins are fixed.
4.3
AD Conversion Characteristics
Ta 20 to 70C, VCC 4.5 to 5.5 V
Parameter
Analog Reference Voltage Supply Analog Input Voltage Range Analog Current for ADREF Total tolerance (excludes quantization error) (Ta 25C, Vcc ADREF 5 V)
Symbol
ADREF ADGND VAIN IREF ET
Min
Vcc 1.5 Vss ADGND
Typ.
Vcc Vss 1.0
Max
Vcc Vss ADREF 1.5 3
Unit
V V V mA LSB
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4.4
Serial Bus Interface Timing
(1) I2C bus Logic Timing
Start Command
tGSTA1 tODAT1
Stop Command
tGSTP1 tGSTP3
SDA
tFSDA tRSDA tRSCL tFSCL
SCL
tGSDA2
tSUODAT
tHDODAT
tHIGH
tLOW
tGSTP2
tCYCSCL
Parameter
SCL cycle SCL low pulse width SCL High pulse width SDA Rising Time SDA Falling Time SCL Rising Time SCL Falling Time (Note 1) (Note 1) (Note 1) (Note 1)
Symbol
tCYCSCL tLOW tHIGH tRSDA tFSDA tRSCL tFSCL tGSTA1 tGSTA2 tODAT1 tSUODAT tHODAT tGSTP1 tGSTP2 tGSTP3
Min
2 /fc
N
Typ.
2N-1/fc
Max
Unit
s s s s s s s
2N-1/fc
The time from start command write to start sheecense Start condition hold time, start generation of the first clock after this Delay time from SCL falling to data output Set up time of data output for SCL rising The time of holding data for SCL rising (Note 2) (Note 2) (Note 3)
2N/fc 2N-1/fc 5/fc 0 4/fc 2N-1/fc 2 /fc 2N-1/fc
N-2
s s s s s s s s
The time from stop command write to starting stop sheecense The time from SDA falling to SCL rising (during stop sheecense) Stop condition set up time
Note 1: The time of rising/falling depend on the feature of bus interface. Note 2: The worst case is at the first bit of slave address. Note 3: The worst case is at the acknowledge bit. Note 4: N: dividing value set by I2CCR1 .
SCK
000 001 010 011 100 101 110 111
N
6 7 8 9 10 11 12 reserved
93CF76-186
2003-03-31
TMP93CF76/CF77/CW76/CU76/CT76
(2) Master SCL output timing The I2CCR1 are used to select a maximum transfer frequency directed from the SCL pin in the master mode.When rising time of the output clock (tRC) is at least 8/fc [s], a high-level time of the output clock (tHC) is tSCL. While the SCL line is fixed to low-level by a slave device,the output clock stops. The first clock (tHC [s] ) after restart is (tSCL/2) (a) In case of tRC
1/FSCL [s] SCL pin (Output) FSCL fSCL tRC
tHC
tSCL. (tSCL 1/fSCL [s] )
(8/fc) [s]
tHC 0.5VCC
tHC
tLC
tLC
tSCL/2 [s]
(b)
In case of tRC
1/FSCL [s]
(8/fc) [s] tHC
tSCL [s] , tLC
tHC tLC
tSCL/2 [s]
SCL pin (Output) FSCL fSCL/1.5 tRC
0.5 VCC
93CF76-187
2003-03-31
TMP93CF76/CF77/CW76/CU76/CT76
(3) Clock Syncro 8 bit SIO mode 1. SCK Input mode Expression Min
25X 6X tSCY2 16X 6X 0
Parameter
SCK cycle SCK falling Latch output data Enable output data SCK raising SCK raising Latch input data Enable input data SCK raising
Symbol
tSCY2 tOHS2 tOSS2 tHSR2 tISS2
Max
Unit
s s s ns ns
Note:
X /fc 2. SCK Output mode Expression Min Max
211X tSCY2 2X 2X 0 s s s s ns 25X 2X
1
Parameter
SCK cycle SCK falling Latch output data Enable output data SCK raising SCK raising Latch input data Enable input data SCK raising
Symbol
tSCY2 tOHS2 tOSS2 tHSR2 tISS2
Unit
Note:
X /fc
1
tSCY2
tOSS2 tISS2
SCK (Input/Output mode)
tOHS2
SO (Output data)
tHSR2
SI (Input data)
93CF76-188
2003-03-31

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